New report says TSMC is on schedule to mass-produce 2nm chips by 2025

By Nick Heyman On Apr 8, 2023

2023 is a historic year in the semiconductor industry. That’s because TSMC and Samsung Foundry are shipping chips made using their respective 3nm process nodes. The smaller the process nodes, the smaller a chip’s feature size which means smaller transistors and higher transistor counts. The more transistors in a chip, the more powerful and energy-efficient that chip is. Apple has reportedly tied up all of TSMC’s first-gen 3nm production and the 3nm A17 Bionic will debut in the iPhone 15 Pro and iPhone 15 Ultra later this year.

TSMC will reportedly start 2nm production in 2025 with enhanced 2nm production starting in 2026

On Friday, a new report from Taiwan online publication MoneyDJ (via Wccftech) says that TSMC will start mass production of 2nm chips starting in 2025. As is typical, an enhanced version of 2nm production called N2P will start in 2026, the year after the first-gen N2 production takes place. This echoes the N3 name for TSMC’s current 3nm production and the N3P name TSMC will call its enhanced 3nm node expected to be available next year.

Wafers for 3nm production are priced at around $20,000 each

TSMC’s N3 yields are said to be improving and with wafers for 3nm production reportedly priced at $20,000 a pop, rising yields are a positive sign. However, Apple will see that price rise by 3% later this year. Apple reportedly pays $110 for each 4nm A16 Bionic chipset and the 3nm A17 Bionic, expected to power the iPhone 15 Pro and iPhone 15 Ultra, could cost $150 for each SoC.

TSMC CEO C.C. Wei has said that he is confident that TSMC will be ready to mass produce 2nm chips by 2025. Today’s report seconds Wei’s opinion and says that the company is on target with its 2nm timeline.

With its second-gen 2nm production to be known as N2P, TSMC will use what is known as BSPD (backside power delivery). This allows transistors to draw electrical power from one side of a chip while the other side will be used to connect transistors with data connection links. This is the same technology that Intel will use in an attempt to regain process leadership from TSMC and Samsung Foundry although Intel calls it PowerVia.

TSMC will also start using gate-all-around (GAA) transistors with its 2nm production. GAA transistors have contact with the channel on all four sides thanks to the use of horizontal nanosheets placed vertically on the chip. This reduces leaks and allows for lower energy consumption. It also increases the drive current leading to improved chip performance.

Samsung Foundry is already using GAA for its 3nm production while TSMC continues to use FinFET transistors on its 3nm chips. FinFET transistors only cover three sides of the channel which results in more leakage. Intel also plans on using GAA which it calls RibbonFET.

Intel is the wild card with its plans to regain process leadership by 2025

Gordon Moore, whose observations led to the creation of Moore’s Law in 1965, recently passed away at the age of 94. But Moore’s Law continues to hang on even though it’s more about the continuing trend of packing more transistors into chips every other year rather than seeing the transistor count double on a biennial basis.

With a market share of 17.3%, Samsung trails TSMC’s 52.9% slice of the chip manufacturing pie. Reportedly, Samsung hopes to triple production capacity for its most advanced chips between now and 2027 in an attempt to reduce that market share gap. And then there is Intel. The wild card here, company CEO Pat Gelsinger says that it will regain process leadership from TSMC and Samsung Foundry by 2025.

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